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Outside of the tight EDA community, you might not have been paying that much attention to ESL. To get started, check it out at Wikipedia / ESL and don't miss Frank Schirrmeister. Schirrmeister is a guru of SystemC / ESL for Synopsys, and his blog is an excellent learning center if you or your management wants to transition up from current design methodologies to ESL. His take on ESL is that one of its major benefits is a software/hardware co-evolution view from the beginning, and one of ESL's promises (along with SystemC) is to allow quick "virtual prototyping" of new chip architectures. The line between hardware and software is blurring, and ESL is a new way to get beyond these antiquated boundaries.

The big recent ESL news at DAC was the 9 June 2008 announcement from Open SystemC Initiative that the Transaction-level Modeling Standard, TLM-2.0, is now complete. The TLM interface standard enables SystemC model interoperability and reuse at the transaction level, providing an essential ESL framework for architecture analysis, software development, software performance analysis, and hardware verification. Again, virtual prototyping seems to be the early push among vendor / customers such as Intel and NXP.

One tools vendor with a clear early lead in SystemC / ESL is, of course, CoWare. They produced a wonderful "on demand" webinar on the new TLM 2.0 standard, which you can view here. They also announced a partnership with Freescale in the automotive space, using ESL 2.0 solutions to deliver triple-core virtual platforms for Freescale and an automotive OEM. It's a practical example of ESL-based technologies helping complex designs, today. Food for thought about how ESL might help you or your customers...

That said, there are certainly vendors that are not ESL per se, but are trying to move the software approach up to a more systematic and system-level view. One to check out, for example, is Bluespec. That company produces an EDA toolset to significantly raise the level of abstraction for hardware design while retaining the ability to automatically synthesize high-quality RTL, without compromising speed, power or area. They just won an FPGA design contest at MEMOCODE 2008; the challenge was to sort large databases of encrypted data using any hardware and software design methodology targeting any field programmable gate array (FPGA) development platform. Details here.

Another leader in FPGA tools is Aldec. They announced their Riviera-PRO™ 2008.06 HDL Simulator. This product is "a behavioral, structural and mixed HDL language simulator for multi-million gate ASIC and FPGA designs. Riviera-PRO 2008.06 includes Verilog® simulation performance enhancements, increased SystemVerilog support, seamless SystemC/C/C++ and HDL co-debugging in common environment and new support for SVA and PSL assertions in the Waveform Viewer." Details here. The great thing about their approach is it is very language- and FPGA vendor-independent, allowing you as the designer a great deal of flexibility and agnosticism about hardware vs. software, and FPGA vendor vs. FPGA vendor. And, they are progressively minded enough to have a fabulous set of free demos and downloads, here.